Monolithic Low Noise and Low Zero-g Offset CMOS/MEMS Accelerometer Readout Scheme
Related Experiment Video
Updated: Feb 1, 2026

Design and Characterization Methodology for Efficient Wide Range Tunable MEMS Filters
Published on: February 4, 2018
1Institute of Electronic Engineering, National Chiao Tung University, Hsinchu 300, Taiwan. thomas.ee02g@nctu.edu.tw.
Abstract:
A monolithic low noise and low zero-g offset CMOS/MEMS accelerometer and readout scheme in standard 0.18 μm CMOS mixed signal UMC process is presented. The low noise chopper architecture and telescopic topology is developed to achieve low noise. The experiments show noise floor is 421.70 μg/√Hz. The whole system has 470 mV/g sensitivity. The power consumption is about 1.67 mW. The zero-g trimming circuit reduces the offset from 1242.63 mg to 2.30 mg.
Related Concept Videos
The Z-Scheme of Electron Transport in Photosynthesis
Karyotyping
Base Excision Repair
The first step of...
Le Chatelier's Principle: Changing Concentration
Self-Discrepancy Theory

