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Residue-Free Fabrication of van der Waals Heterostructures of Two-Dimensional Materials
Published on: July 18, 2025
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Vertical WS2/SnS2 van der Waals Heterostructure for Tunneling Transistors
Jiaxin Wang1, Rundong Jia1, Qianqian Huang2
1Key Laboratory of Microelectronic Devices and Circuits (MOE), Institute of Microelectronics, Peking University, Beijing, 100871, China.
Scientific Reports
|December 12, 2018
Summary
This study presents an optimized 2D-2D heterostructure for tunneling transistors, achieving a high on-off ratio and steeper subthreshold slope. The novel WS₂/SnS₂ tunneling transistor demonstrates potential for energy-efficient electronics.
Area of Science:
- Materials Science
- Condensed Matter Physics
- Nanotechnology
Background:
- Two-dimensional (2D) transition metal dichalcogenides (TMD) van der Waals heterostructures are promising for energy-efficient electronics.
- Tunnel junction transistors offer tunable band alignment and pristine interfaces for enhanced performance.
Purpose of the Study:
- To engineer an optimal 2D-2D heterostructure for tunneling transistors, considering electrical properties and material stability.
- To address challenges in band alignment and contact resistance for improved device integration.
Main Methods:
- Theoretical design and engineering of 2D-2D heterostructures.
- Development of a new dry transfer technique for vertical stacking.
- Fabrication and characterization of WS₂/SnS₂ heterostructure-based tunneling transistors.
Main Results:
- First fabrication of a WS₂/SnS₂ heterostructure tunneling transistor.
- Superior performance including a steeper subthreshold slope and on-off current ratio > 10⁶.
- Observation of negative differential resistance.
Conclusions:
- The WS₂/SnS₂ heterostructure shows great potential for advanced tunneling transistors.
- This work guides the development of energy-efficient electronics using 2D layered semiconductors.
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