A Novel Defect Tolerance Scheme for Nanocrossbar Architectures with Enhanced Efficiency

Area of Science:

• Nanotechnology
• Materials Science
• Computer Engineering

Background:

• Semiconductor industry faces challenges meeting Moore's Law demands.
• Molecular switch-based nanodevices offer ultimate miniaturization potential.
• Bottom-up self-assembly manufacturing limits external intervention, causing yield loss from defects.

Purpose of the Study:

• To develop a defect-unaware fault tolerance scheme for nanocrossbar architectures.
• To improve manufacturing yield for molecular switch-based nanodevices.
• To address the limitations of traditional test-and-throw approaches for defective nanodevices.

Main Methods:

• Utilized a bipartite graph analogy for crossbar architectures.
• Developed a novel defect-unaware fault tolerance algorithm.
• Implemented an iterative node elimination strategy.

Main Results:

• The new algorithm eliminates multiple nodes per iteration, accelerating defect-free subcrossbar formation.
• Demonstrated faster defect removal compared to existing algorithms.
• Achieved improved yield in most cases compared to current defect-unaware fault-tolerant methods.

Conclusions:

• The developed fault tolerance scheme enhances the viability of molecular switch nanodevices.
• Faster and more efficient defect management is crucial for nanodevice manufacturing.
• This approach offers a promising solution for increasing yield in nanodevice production.