Fabrication and Packaging of CMUT Using Low Temperature Co-Fired Ceramic.

Capacitive micromachined ultrasonic transducers (CMUTs) are widely used in imaging and sensing applications. However, packaging and integration of CMUTs with integrated circuits (ICs) remain challenging due to material compatibility and miniaturization constraints. Prior research has shown that direct integration of CMUTs and ICs often introduces reliability and thermal issues. No prior work had resolved the issue of indirect integration while maintaining high performance. This gap motivated the exploration of alternative packaging strategies. Low temperature co-fired ceramic (LTCC) has emerged as a promising substrate material due to its high conductivity and compatibility with micromachining. However, the use of LTCC for CMUT packaging had not been fully evaluated. This paper addresses the need for a scalable and reliable fabrication method. The study introduces a novel approach using anodically bondable LTCC with gold vias. The method aims to simplify integration while preserving device functionality.

The goal of this research is to develop a fabrication and packaging process for CMUTs using LTCC as a substrate. The process must enable indirect integration with ICs to avoid direct bonding challenges. The study focuses on anodically bonding LTCC with silicon-on-insulator (SOI) wafers. This approach allows for the creation of CMUTs with varying membrane sizes. The researchers propose using LTCC vias to establish electrical connections. The study also evaluates the feasibility of using lateral side vias for CMUT-IC integration. The process must be scalable for high-density CMUT arrays. The authors aim to demonstrate that this method can reduce packaging complexity and improve device reliability.

The fabrication process involves anodic bonding of LTCC with SOI wafers containing gold vias. The SOI wafers are used to create CMUT membranes of different radii. Wet etching is applied to form LTCC vias and CMUT cavities. Bottom electrodes are patterned on the remaining vias after etching. The top electrode is formed using the highly conductive silicon layer of the SOI wafer. Gold bumps are micromachined on the silicon part for bonding. Anodic bonding connects the gold vias and bumps during fabrication. Three parameters—static displacement, admittance, and infrared imaging—are used to assess bonding quality. A novel packaging process is described for CMUT-IC integration using lateral side vias.

CMUTs with membrane radii of 24 µm, 25 µm, 36 µm, 40 µm, and 60 µm were successfully fabricated. The membrane thickness was measured at 2.6 µm for experimental analysis. Anodic bonding was confirmed using infrared imaging and admittance measurements. The bonding process achieved reliable electrical connections between top and bottom electrodes. Lateral side vias were micromachined to enable indirect CMUT-IC integration. The catheter was assembled at the backside of the CMUT for packaging. The IC was mounted on the catheter using flip-chip bonding. Bond resistance between the IC and catheter was measured to evaluate connection reliability. The results suggest that the LTCC-based method supports high-density CMUT arrays. The approach eliminates issues associated with direct integration methods.

The authors propose that the LTCC-based fabrication and packaging method is a viable solution for CMUT-IC integration. The use of lateral side vias enables indirect connection without compromising performance. The process supports high-density CMUT arrays for miniature packaging. The study suggests that this method reduces thermal and mechanical stress during integration. The bonding performance was validated using bond resistance measurements. The approach eliminates the need for direct bonding between CMUTs and ICs. The authors suggest that this method improves reliability and scalability. The findings may support future development of compact ultrasonic imaging systems.