A High-Performance Rectangular Gate U Channel FETs with Only 2-nm Distance between Source and Drain Contacts

Area of Science:

• Semiconductor device physics
• Integrated circuit design
• Nanoelectronics

Background:

• Scaling challenges in traditional Field-Effect Transistors (FETs) necessitate novel device architectures.
• Achieving high performance at extremely small dimensions requires innovative gate control and contact placement.

Purpose of the Study:

• To propose and investigate a novel Rectangular Gate U Channel FET (RGUC FET) for high-performance integrated circuits.
• To explore the feasibility of RGUC FETs for applications requiring extremely short source/drain (S/D) contact distances.
• To analyze the impact of key design parameters on the electrical properties of the RGUC FET.

Main Methods:

• Device fabrication conceptualization focusing on gate contact placement in a spacer layer.
• Electrical property investigation through systematic analysis of design parameters.
• Performance verification using quantum simulation.

Main Results:

• The RGUC FET demonstrates nearly ideal subthreshold characteristics even when S/D contacts are reduced to 2nm.
• The proposed gate structure simplifies fabrication by avoiding recessed regions.
• Quantum simulations confirm the device's electrical properties and suitability for integration.

Conclusions:

• The RGUC FET is a promising architecture for next-generation integrated circuits demanding extreme S/D integration.
• Its unique structural design offers advantages over other non-planar channel multi-gate FETs for higher integration.
• The device shows excellent performance scalability for future nanoelectronic applications.