A Successive Approximation Time-to-Digital Converter with Single Set of Delay Lines for Time Interval Measurements

Area of Science:

• * Digital electronics and integrated circuit design.
• * Signal processing and data conversion.

Background:

• * Time-to-Digital Converters (TDCs) are crucial for precise timing measurements.
• * Successive Approximation TDCs (SA-TDCs) offer a balance of resolution and speed.
• * Existing SA-TDC designs often face challenges with circuit complexity and area.

Purpose of the Study:

• * To provide a tutorial overview of Successive Approximation TDCs (SA-TDCs).
• * To optimize SA-TDC design for reduced complexity, smaller die area, and improved performance.
• * To introduce a novel feedforward architecture for enhanced SA-TDC design.

Main Methods:

• * Utilized binary-scaled delay lines within a feedforward architecture.
• * Developed a complexity reduction technique by removing one set of delay lines.
• * Implemented an 8-bit SA-TDC in 180 nm CMOS technology.

Main Results:

• * Achieved a complexity reduction of close to 50% for 12-bit resolution.
• * Demonstrated an 8-bit SA-TDC with a quantization step of 25 ps.
• * Verified performance improvements through circuit implementation.

Conclusions:

• * The proposed SA-TDC design offers significant advantages in terms of complexity and area.
• * The optimized design maintains or improves converter performance.
• * This work contributes a practical and efficient approach to SA-TDC design.