An Efficient Hardware Architecture for Template Matching-Based Spike Sorting

This paper presents an efficient hardware architecture for the design and implementation of a spike sorting system using online template matching. Over the past decade, various spike sorting algorithms have been proposed; however, due to their computational complexity, they may not be suitable for implantable devices that have stringent area and power consumption requirements. We first developed a software-based spike sorting system in both floating-point and fixed-point representations. Then, we used our developed software-based spike sorting system for: 1) studying various neural signal processing algorithms and assessing their feasibility for efficient hardware implementations; and 2) offline processing of previously recorded neural data and extracting the threshold data and spike templates for configuring our spike sorting hardware architecture. The characteristics and implementation results of the designed spike sorting system on a Xilinx Artix-7 A200TFBG676-2 field-programmable gate array are presented. The application-specific integrated circuit (ASIC) implementation of the designed spike sorting system is estimated to occupy 0.3 mm². Postlayout synthesis and simulation shows that the ASIC implementation will dissipate 64 nW from a 0.25-V supply, while operating at a 24-kHz frequency in a standard 45-nm CMOS technology. Compared to the previously published work, our ASIC implementation consumes 96.8% less power, while maintaining a comparable sorting accuracy. Moreover, our design can run at a higher clock frequency and uses fewer hardware resources, while achieving a 168% reduction in output data rate when comparing the raw data sampling rate and the sorted spike output rate and, yet, offers comparable spike sorting accuracy.