An Efficient Hardware Architecture for Template Matching-Based Spike Sorting.

Area of Science:

• Neuroscience
• Electrical Engineering
• Computer Engineering

Background:

• Spike sorting algorithms are computationally complex, limiting their use in power-constrained implantable devices.
• Efficient hardware architectures are needed for real-time neural data processing in miniaturized systems.

Purpose of the Study:

• To design and implement an efficient hardware architecture for a spike sorting system using online template matching.
• To assess the feasibility of neural signal processing algorithms for hardware implementation.
• To develop a low-power, high-accuracy spike sorting system for implantable devices.

Main Methods:

• Developed a software-based spike sorting system (floating-point and fixed-point).
• Utilized the software system for algorithm feasibility studies and offline data processing to extract spike templates.
• Designed and implemented the hardware architecture on a Xilinx Artix-7 field-programmable gate array.
• Simulated application-specific integrated circuit (ASIC) implementation.

Main Results:

• The ASIC implementation occupies 0.3 mm² and dissipates 64 nW from a 0.25-V supply.
• Operates at 24 kHz in 45-nm CMOS technology.
• Achieves 96.8% less power consumption than prior work with comparable accuracy.
• Offers higher clock frequency, fewer hardware resources, and a 168% reduction in output data rate.

Conclusions:

• The proposed hardware architecture offers a significant advancement in power efficiency and data rate reduction for spike sorting.
• This design is highly suitable for resource-limited implantable neural recording systems.
• The system provides a compelling balance of low power, high speed, and accurate spike sorting.