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Transient Analysis of Tunnel Field-Effect Transistor with Raised Drain
Jang Hyun Kim1, Hyun Woo Kim1, Seong-Su Shin2
1Department of Electrical and Computer Engineering, Seoul National University, Seoul, 08826, South Korea.
Abstract:
This paper investigates the electrical performance of a proposed tunnel field-effect transistor (TFET) via transient analysis. The proposed TFET has three features: a SiGe channel, a fin structure, and an elevated drain. As the SiGe channel and fin structure make a small tunnel resistance, the ONstate current can be increased. In addition, an elevated drain can suppress an ambipolar current (IAMB). The transient characteristics should be confirmed in terms of inverter switching for the high applicability of the proposed device to the logical circuit. The analysis is verified through technology computer-aided design (TCAD) simulations calibrated with rigorously fabricated devices. Based on the simulation results, we conclude that the proposed TFET shows better ON/OFF transient characteristics when compared to conventional TFETs and the small gate-to-drain capacitance (CGD) can improve the transient characteristics in TFET.
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