Simulation for Electrical Performances of the Capacitorless Dynamic Random Access Memory Based on Junctionless...

Area of Science:

• Semiconductor device physics
• Solid-state electronics
• Materials science

Background:

• Traditional dynamic random access memory (DRAM) requires capacitors for data storage, leading to scalability challenges.
• Capacitorless DRAM designs offer potential for higher density and reduced power consumption.
• Heterojunctions in field-effect transistors (FETs) are explored for novel memory applications.

Purpose of the Study:

• To propose and simulate a novel junctionless, fin-type FET-based capacitorless dynamic random access memory (1T-DRAM).
• To investigate the charge storage mechanism utilizing a silicon-germanium heterojunction.
• To analyze and optimize the device performance for practical memory applications.

Main Methods:

• Three-dimensional technology computer-aided design (3D TCAD) simulations were employed.
• Device operation principles, including programming and data retention, were modeled.
• Performance metrics such as retention time and data margin were evaluated.

Main Results:

• A junctionless, fin-type FET structure with a silicon-germanium storage region was designed.
• The heterojunction's band discontinuity creates a potential well for efficient hole storage.
• Simulations demonstrated a promising retention time of 161 ms at a 50% data margin.

Conclusions:

• The proposed 1T-DRAM architecture offers a viable solution for high-density memory.
• The silicon-germanium heterojunction effectively enables capacitorless data storage.
• Further optimization of this device structure could lead to advanced memory technologies.