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Published on: November 7, 2016
Design Optimization of InGaAs/GaAsSb-Based P-Type Gate-All-Around Arch-Shaped Tunneling Field-Effect Transistor
Bo Gyeong Kim1, Jae Hwa Seo1, Young Jun Yoon1
1School of Electronics Engineering, Kyungpook National University, Daegu, 41566, South Korea.
Abstract:
In this work, an InGaAs/GaAsSb-based P-type gate-all-around (GAA) arch-shaped tunneling fieldeffect transistor (TFET) was designed and analyzed using technology computer-aided design (TCAD) simulations. The device performance was investigated in views of the on-state current (Ion), subthreshold swing (SS), and Ion/Ioff ratio. For high current drivability, InGaAs/GaAsSb heterojunction is used to form the broken bandgap. Owing to the GAA arch-shaped structure of the TFET, the tunneling region between source and channel extended, thus Ion and SS are improved. However, it has some performance variations that are related with the height of the source region (Hsource), the epitaxially grown thickness of the channel (tepi), and the height of the drain region (Hdrain). Therefore, we performed a design optimization of the proposed device with the variables of Hsource, tepi, and Hdrain. The designed and optimized InGaAs/GaAsSb-based P-type GAA arch-shaped TFET demonstrated an Ion of 215 μA/μm SS of 18 mV/dec and Ion/Ioff of 1.64 × 1012.
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