Device Optimization of Nano-Plate Transistors for 3.5 nm Technology Node

Area of Science:

• Semiconductor device physics
• Advanced transistor technology

Background:

• Scaling of transistors to smaller technology nodes like 3.5 nm presents challenges in maintaining performance.
• Lateral gate-all-around nano-plate FETs (NP-FETs) are a key area of research for future integrated circuits.

Purpose of the Study:

• To optimize 3.5 nm NP-FETs and compare their electrostatic characteristics with 7 nm and 5 nm nodes.
• To investigate methods for improving the performance, particularly RC-delay, of scaled NP-FETs.

Main Methods:

• 3D Technology Computer-Aided Design (TCAD) simulations were employed to analyze transistor electrostatics.
• Physical parameters including channel radius and thickness were optimized for the 3.5 nm node NP-FETs.
• Trenched contact and channel strain engineering techniques were applied to further enhance performance.

Main Results:

• Optimized 3.5 nm NP-FETs demonstrated superior gate controllability and subthreshold swing (S.S.) due to reduced channel thickness.
• Parasitic resistance, capacitance, and low bias conditions limited the on-current and RC-delay performance of the scaled devices.
• Trenched contact method improved RC-delay by ~18%, while strain engineering achieved ~14% improvement.

Conclusions:

• While smaller channel thickness enhances gate control in 3.5 nm NP-FETs, parasitic effects limit on-current and delay performance.
• Trenched contact and channel strain engineering are effective strategies to overcome performance limitations and improve RC-delay in advanced nano-plate transistors.