ASIC modelling of SENSE for parallel MRI.

Area of Science:

• Medical Imaging
• Hardware Acceleration
• Biomedical Engineering

Background:

• Magnetic Resonance Imaging (MRI) is crucial for medical diagnostics.
• Parallel MRI (pMRI) accelerates imaging by acquiring undersampled data with multiple coils.
• Offline reconstruction algorithms are typically used to generate full images in pMRI.

Purpose of the Study:

• To develop and evaluate an Application Specific Integrated Circuit (ASIC) hardware description language (HDL) model for the SENSE pMRI reconstruction algorithm.
• To enable real-time image reconstruction directly on the MRI data acquisition module.
• To compare the performance of the proposed ASIC architecture against existing reconstruction methods.

Main Methods:

• An ASIC HDL architecture for the SENSE algorithm was designed and modeled.
• The ASIC model was compared with SENSE implementations on FPGAs, multi-core CPUs, and GPUs.
• Validation was performed using simulated brain data (8-channel) and a human cardiac dataset (20-channel).
• Image quality was assessed using Artifact Power, Peak Signal-to-Noise Ratio (PSNR), and Structural Similarity Index (SSIM).

Main Results:

• The ASIC-based SENSE reconstruction achieved significant speedups: ~8000x faster than multi-core CPU, ~700x faster than GPU, and ~16x faster than FPGA.
• Reconstructed images demonstrated high quality, with Artifact Power of 0.0098, PSNR of 53.4, and SSIM of 0.871.
• The proposed architecture is suitable for on-device image reconstruction within the MRI scanner.

Conclusions:

• The developed ASIC HDL model for SENSE reconstruction offers substantial performance improvements over conventional methods.
• This hardware acceleration enables faster image reconstruction directly on the data acquisition system.
• The findings pave the way for enhanced speed and potential for portable MRI scanners.