A 6.6 ps RMS resolution time-to-digital converter using interleaved sampling method in a 28 nm FPGA

Based on the adaptive logic module structure implemented in a 28 nm field programmable gate array (FPGA), we propose an interleaved sampling method, together with bin realignment operation, to enable time-to-digital converter (TDC) implementation. The tap status is sampled twice in a single physical channel, meaning that TDC precision beyond the cell delay limit can be anticipated. Two TDC channels were implemented in a 28 nm Cyclone-V FPGA, and the effectiveness of the proposed method was evaluated. After calibration, the TDC produced a timing resolution of 6.6 ps root mean square or 5.8 ps per least significant bit.