Damage-free mica/MoS₂ interface for high-performance multilayer MoS₂ field-effect transistors

For top-gated MoS₂ field-effect transistors, damaging the MoS₂ surface to the MoS₂ channel are inevitable due to chemical bonding and/or high-energy metal atoms during the vacuum deposition of gate dielectric, thus leading to degradations of field-effect mobility (μ _FE) and subthreshold swing (SS). A top-gated MoS₂ transistor is fabricated by directly transferring a 9 nm mica flake (as gate dielectric) onto the MoS₂ surface without any chemical bonding, and exhibits excellent electrical properties with an on-off ratio of ∼10⁸, a low threshold voltage of ∼0.2 V, a record μ _FE of 134 cm² V^-1 s^-1, a small SS of 72 mV dec^-1 and a low interface-state density of 8.8 × 10¹¹ cm^-2 eV^-1, without relying on electrode-contact engineered and/or phase-engineered MoS₂. Although the equivalent oxide thickness of the mica dielectric is in the sub-5 nm regime, enhanced stability characterized by normalized threshold voltage shift (1.2 × 10^-2 V MV^-1 cm^-1) has also been demonstrated for the transistor after a gate-bias stressing at 4.4 MV cm^-1 for 10³ s. All these improvements should be ascribed to a damage-free MoS₂ channel achieved by a dry transfer of gate dielectric and a clean and smooth surface of the mica flake, which greatly decreases the charged-impurity and interface-roughness scatterings. The proposed transistor with low threshold voltage and high stability is highly desirable for low-power electronic applications.