Accurate Threshold Voltage Reliability Evaluation of Thin Al₂O₃ Top-Gated Dielectric Black Phosphorous FETs Using...

Few-layer black phosphorus (BP) has attracted significant interest in recent years due to electrical and photonic properties that are far superior to those of other two-dimensional layered semiconductors. The study of long term electrical stability and reliability of black phosphorus field effect transistors (BP-FETs) with technologically relevant thin, and device-selective, gate dielectrics, stressed under realistic (closer to operation) bias and measured using state-of-the-art ultrafast reliability characterization techniques, is essential for their qualification and use in different applications. In this work, air-stable BP-FETs with a thin top-gated dielectric (15 nm Al₂O₃, SiO₂ equivalent thickness of 5 nm) were fabricated and comprehensively characterized for threshold voltage ( V_th) instability under negative gate bias stress at various measurement delays ( t_m), stress biases ( V_GSTR), temperatures ( T), and stress times ( t_str) for the first time. Thin top-gated oxide enables low V_GSTR that is closer to the operating condition and ultrafast V_th measurements with low delay ( t_m = 10 μs, due to high drain current) that ensure minimal recovery. The resultant time kinetics of V_th degradation (Δ V_th) shows fast saturation at longer stress times and low-temperature activation energy. V_th instability in these top-gated devices is suggested to be dominated by hole trapping, which is modeled using first-order equations at different V_GSTR and T. It is shown that measurements using larger t_m show lower degradation magnitude that do not saturate due to recovery artifacts and give inaccurate estimation of hole trap densities. Conventional, thick, and global back-gated oxide BP-FETs were also fabricated and characterized for varying t_m (1 ms being the lowest due to a low drain current level for thick oxide), V_GSTR, and T to benchmark our top-gated results. Nonsaturating Δ V_th in the back-gated devices is shown to result from recovery artifacts due to the large t_m (1 ms and greater) values. Finally, using a V_GSTR and T-dependent first-order model, we show that the top-gated Al₂O₃ BP-FETs with scaled gate oxide thickness can match state-of-the-art Si reliability specifications at operating voltage and room/elevated temperature.