Vertically Integrated Dual-Memtransistor Enabled Reconfigurable Heterosynaptic Sensorimotor Networks and In-Memory...

Area of Science:

• Materials Science
• Electrical Engineering
• Computer Science

Background:

• Neuromorphic computing demands area-efficient architectures for high-speed data processing.
• Existing solutions often struggle with latency and power consumption for large datasets.

Purpose of the Study:

• To develop a compact, vertically integrated transistor architecture for advanced neuromorphic in-memory computing.
• To demonstrate the device's capability in emulating biological learning mechanisms and performing logic operations.

Main Methods:

• Fabrication of a vertically integrated/stratified field-effect transistor (VSFET) using 2D MoS2 and In2Se3 channels.
• Characterization of electrostatic coupling effects and transistor synaptic behaviors.
• Implementation and testing of artificial neural network (ANN) and spiking neural network (SNN) learning paradigms.
• Demonstration of Boolean logic gate reconfigurability.

Main Results:

• The VSFET exhibits hysteretic characteristics due to electrostatic coupling between MoS2 and In2Se3 channels.
• The MoS2 memtransistor successfully emulates homosynaptic plasticity with high accuracy and low nonlinearity.
• Complex heterosynaptic cooperation and competition behaviors are mimicked, replicating Aplysia gill withdrawal reflex.
• Ultralow power consumption is achieved for on-chip learning and synaptic emulation.
• The VSFET demonstrates logic reconfigurability for versatile computing applications.

Conclusions:

• The VSFET offers a promising, area-efficient platform for neuromorphic in-memory computing.
• The device effectively emulates biological learning and synaptic plasticity, paving the way for advanced AI hardware.
• The demonstrated logic reconfigurability adds significant design flexibility for future computing technologies.