Effect of device design on charge offset drift in Si/SiO₂ single electron devices

Area of Science:

• Solid State Physics
• Quantum Computing Hardware
• Nanoscale Electronics

Background:

• Charge offset drift is a low-frequency time instability in single electron devices (SEDs).
• This instability, characterized by fluctuations and jumps in charge offset, impacts device performance.
• Current understanding often attributes drift to intrinsic material properties.

Purpose of the Study:

• To investigate the effect of a poly-Si top gate on charge offset drift in Si/SiO2 SEDs.
• To determine if device design can mitigate charge offset drift.
• To provide insights for developing more stable SEDs for advanced applications.

Main Methods:

• Experimental measurement of low-frequency charge offset drift in Si/SiO2 SEDs.
• Comparison of devices with and without an integrated poly-Si top gate.
• Analysis of capacitance changes (mutual capacitance Cm and defect capacitance Cd) influenced by the top gate.

Main Results:

• SEDs incorporating a poly-Si top gate exhibit substantially reduced charge offset drift.
• A two-fold decrease in fluctuations and fewer isolated jumps were observed with the top gate.
• Electrostatic effects, including reduced Cm and increased Cd, explain the observed drift reduction.

Conclusions:

• Device design, specifically the addition of a poly-Si top gate, plays a crucial role in controlling charge offset drift.
• Findings challenge the notion that drift is solely determined by intrinsic material properties.
• This work is vital for advancing SEDs in quantum information, metrology, and other fields sensitive to charge noise.