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A 678-μW Frequency-Modulation-Based ADC With 104-dB Dynamic Range in 44-kHz Bandwidth.

Julian Warchall1, Shiva Kaleru1, Nidhi Jayapalan1

  • 1The authors are with the Department of Electrical and Computer Engineering, University of California at San Diego, La Jolla, CA 92093 USA.

IEEE Transactions on Circuits and Systems. II, Express Briefs : a Publication of the IEEE Circuits and Systems Society
|July 10, 2019
PubMed
Summary
This summary is machine-generated.

This study introduces a novel frequency-modulation analog-to-digital converter (FM ADC) achieving high dynamic range and power efficiency. Its unique architecture offers a promising alternative to traditional converters for advanced applications.

Keywords:
ADCFMSARVCOlow power

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Area of Science:

  • Electrical Engineering
  • Signal Processing
  • Integrated Circuit Design

Background:

  • Traditional analog-to-digital converters (ADCs) face challenges in achieving high dynamic range (DR) and power efficiency simultaneously, especially in advanced semiconductor processes.
  • Delta-sigma converters are common for high-resolution applications but can be power-intensive and complex.
  • Frequency modulation (FM) systems offer inherent coding gain through bandwidth expansion, a property not fully exploited in ADC design.

Purpose of the Study:

  • To present a novel frequency-modulation-based analog-to-digital converter (FM ADC) architecture.
  • To demonstrate high dynamic range and power efficiency by leveraging analog domain bandwidth expansion and digital demodulation.
  • To offer a competitive alternative to existing high-DR conversion techniques, particularly delta-sigma converters.

Main Methods:

  • The proposed FM ADC architecture utilizes a sinusoidal output voltage-controlled oscillator (VCO).
  • A low-resolution successive approximation register (SAR) ADC samples signals in the FM domain.
  • Digital signal processing (DSP) is employed for FM demodulation to recover high-resolution analog input samples.

Main Results:

  • The implemented FM ADC achieves a dynamic range (DR) of 104 dB.
  • It demonstrates a signal-to-noise ratio (SNR) of 99 dB and a signal-to-noise-and-distortion ratio (SNDR) of 71 dB within a 44-kHz bandwidth.
  • The converter achieves this performance while dissipating only 678 μW of power, implemented in 0.5-mm² of 65-nm CMOS technology.

Conclusions:

  • The FM ADC architecture effectively leverages analog domain processing for performance and digital domain processing for power efficiency.
  • This novel approach provides a viable and competitive alternative to delta-sigma converters for high dynamic range applications.
  • The design is suitable for implementation in advanced process nodes, offering a new direction in high-performance data conversion.