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An Energy Efficient and Temperature Stable Digital FLL-based Wakeup Timer with Time-Domain Temperature Compensation.

Minyoung Song1, Ming Ding2, Yao-Hong Liu2

  • 1Department of Electrical Engineering and Computer Science, Daegu Gyeongbuk Institute of Science and Technology (DGIST), Daegu, South Korea.

IEEE Transactions on Circuits and Systems. II, Express Briefs : a Publication of the IEEE Circuits and Systems Society
|July 4, 2024
PubMed
Summary
This summary is machine-generated.

This study introduces a digital frequency-locked loop (DFLL)-based wakeup timer that uses temperature compensation to maintain stable operating frequency. This innovation ensures precise timing for low-power applications across various temperatures.

Keywords:
Frequency-locked loop (FLL)Internet of things (IoT)Low-powerOscillatorReal-time clock (RTC)Temperature sensingWakeup timerwake-up timer

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Area of Science:

  • Integrated Circuits
  • Low-Power Electronics
  • Embedded Systems

Background:

  • Accurate timing is crucial for low-power embedded systems, but temperature variations can significantly impact oscillator and timer frequencies.
  • Existing temperature compensation techniques often introduce considerable power and hardware overhead.
  • Digital intensive frequency-locked loops (DFLLs) offer a flexible platform for timing applications.

Purpose of the Study:

  • To develop an on-chip digital intensive frequency-locked loop (DFLL)-based wakeup timer with effective time-domain temperature compensation.
  • To achieve precise frequency stability across a wide temperature range with minimal power and hardware overhead.
  • To demonstrate the feasibility of a novel temperature compensation strategy using complementary resistors.

Main Methods:

  • Implemented a DFLL-based wakeup timer incorporating an embedded temperature sensor.
  • Utilized the deterministic temperature characteristics of complementary resistors for frequency stabilization.
  • Modulated the activation time window of complementary resistors to compensate for temperature-induced frequency drift.
  • Fabricated the chip in 40 nm CMOS technology.

Main Results:

  • Achieved a fine trimming step of ± 1 ppm, resulting in a frequency error below ± 20 ppm after trimming.
  • Demonstrated temperature stability of 8 ppm/ºC over a temperature range of -40ºC to 80ºC.
  • Attained high energy efficiency of 0.9 pJ/cycle.
  • Showcased negligible power (2%) and hardware overhead (<1%) by reusing the DFLL structure for temperature sensing.

Conclusions:

  • The proposed DFLL-based wakeup timer with time-domain temperature compensation effectively stabilizes operating frequency across temperature variations.
  • This approach offers a low-overhead, energy-efficient solution for precise timing in embedded systems.
  • The technique of exploiting complementary resistor characteristics presents a viable method for background temperature sensing and compensation.