MorphIC: A 65-nm 738k-Synapse/mm ² Quad-Core Binary-Weight Digital Neuromorphic Processor With Stochastic...

Area of Science:

• Neuromorphic Engineering
• Artificial Intelligence Hardware
• Digital Signal Processing

Background:

• Weight quantization in neural networks enhances resource and power efficiency.
• Binary weights and spiking neural networks (SNNs) offer further reductions but face challenges with on-chip learning and synapse density.
• On-chip learning is crucial for power-constrained applications.

Purpose of the Study:

• To develop a power- and area-efficient SNN processor leveraging on-chip online learning with binary weights.
• To demonstrate a novel digital neuromorphic processor, MorphIC, designed for high synapse density and efficient learning.

Main Methods:

• Designed MorphIC, a quad-core binary-weight digital neuromorphic processor.
• Integrated a stochastic spike-driven synaptic plasticity (S-SDSP) learning rule.
• Implemented a hierarchical routing fabric for scalable interconnections.

Main Results:

• Achieved 738k synapses/mm² density on a 2.86 mm² chip (65-nm CMOS).
• Demonstrated an order-of-magnitude improvement in area-accuracy tradeoff on MNIST classification.
• Showcased no energy-accuracy tradeoff penalty compared to prior SNNs.

Conclusions:

• MorphIC offers a significant advancement in area- and energy-efficient neuromorphic computing.
• The processor effectively combines binary weights, on-chip learning, and high synapse density.
• This work paves the way for more powerful and efficient edge AI devices.