A Multi-Method Simulation Toolbox to Study Performance and Variability of Nanowire FETs.

Area of Science:

• Computational Physics
• Semiconductor Device Modeling
• Materials Science

Background:

• Accurate simulation of advanced semiconductor devices is crucial for performance and scalability.
• Understanding variability sources is key to optimizing nanoscale transistor design.
• Existing models may not fully capture the complex interplay of factors in modern transistors.

Purpose of the Study:

• To introduce a novel 3D multi-method simulation toolbox for characterizing semiconductor devices.
• To evaluate the performance, scalability, and variability of a 10 nm gate-all-around (GAA) field-effect transistor (FET).
• To identify critical regions sensitive to specific variability sources.

Main Methods:

• Development of an in-house 3D multi-method semi-classical/classical simulation toolbox.
• Benchmark simulation of a 10 nm gate length Si GAA FET.
• Analysis of device performance metrics including on-current (I ON), off-current (I OFF), and I ON / I OFF ratio.
• Quantification of threshold voltage standard deviation due to multiple variability sources.
• Generation of fluctuation sensitivity maps to pinpoint critical device regions.

Main Results:

• The simulated 10 nm GAA FET achieved an I OFF of 0.03 μA/μm and an I ON of 1770 μA/μm, yielding an I ON / I OFF ratio of 6.63 × 10^4.
• This ratio is 27% higher than a comparable 10.7 nm Si FinFET, with a subthreshold slope (SS) of 71 mV/dec.
• The threshold voltage standard deviation was 55.5 mV, significantly higher than the FinFET's 30 mV, attributed to line-edge roughness, metal grain granularity, and random dopants.
• Sensitivity maps revealed that the on-current is highly susceptible to line-edge roughness near the source-gate junction and metal grains near the gate-source proximity.

Conclusions:

• The developed 3D toolbox effectively characterizes advanced semiconductor devices, highlighting performance and variability trade-offs.
• The 10 nm GAA FET demonstrates superior on/off current ratios but increased sensitivity to variability compared to FinFETs.
• Identifying critical regions for variability mitigation is essential for future nanoscale transistor development.