Spike Counts Based Low Complexity SNN Architecture With Binary Synapse.

Area of Science:

• Computer Engineering
• Artificial Intelligence
• Neuroscience

Background:

• Spike Neural Networks (SNNs) offer potential for energy-efficient AI computation.
• Traditional SNN designs often face challenges in hardware implementation due to complexity.
• Reducing computational complexity is crucial for practical SNN deployment.

Purpose of the Study:

• To present an energy and area-efficient SNN processor.
• To introduce hardware-friendly complexity reduction techniques for SNNs.
• To enable low-cost SNN design for both learning and inference.

Main Methods:

• Developed a novel spike counts-based unsupervised learning method.
• Utilized pre- and post-synaptic spike counts to reduce synaptic weight bit-width and updates.
• Implemented an accumulation-based computing scheme for energy-efficient inference.
• Incorporated computation skip schemes to eliminate redundant calculations.

Main Results:

• Designed and implemented an SNN processor using 65 nm CMOS technology.
• Achieved 87.4% recognition accuracy on the MNIST dataset.
• Employed only 1-bit 230k synaptic weights and 400 excitatory neurons.
• Demonstrated low energy consumption: 0.26 pJ/SOP (inference) and 1.42 pJ/SOP (learning).

Conclusions:

• The proposed spike counts-based methods significantly reduce SNN complexity.
• The developed SNN processor is both energy and area efficient.
• This work paves the way for practical, low-cost SNN hardware implementations.