A Power and Area Efficient CMOS Stochastic Neuron for Neural Networks Employing Resistive Crossbar Array.

Area of Science:

• Electronics Engineering
• Computer Science
• Materials Science

Background:

• Resistive computing offers potential for energy-efficient neural networks.
• Traditional neural network hardware often relies on power-intensive converters.
• Stochastic computing presents an alternative paradigm for hardware acceleration.

Purpose of the Study:

• To present a power and area efficient CMOS stochastic neuron for resistive computing device-based neural networks.
• To enable simultaneous quantization and activation using a single dynamic comparator.
• To introduce a network learning method that minimizes computation time with minimal accuracy degradation.

Main Methods:

• Designed a stochastic neuron using a single dynamic comparator for integrated quantization and activation.
• Eliminated the need for power-hungry analog-to-digital and digital-to-analog converters.
• Developed a network learning algorithm employing a noisy sigmoid function to optimize computation time.

Main Results:

• A prototype neuron chip was fabricated using a 0.18μm CMOS process.
• The chip successfully demonstrated the stochastic neuron's performance.
• Network simulations verified the efficacy of the learning method with minimal accuracy loss.

Conclusions:

• The proposed stochastic neuron offers a power and area efficient solution for resistive computing neural networks.
• Integrating quantization and activation functions reduces hardware complexity and power consumption.
• The presented learning method effectively balances computation time and accuracy in stochastic neural networks.