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Application of Deep Compression Technique in Spiking Neural Network Chip
IEEE Transactions on Biomedical Circuits and Systems
|November 13, 2019
Summary
A novel spiking neural network processor utilizes deep compression to reduce hardware requirements by 16x while maintaining accuracy. This energy-efficient chip achieves high performance for handwritten digit recognition tasks.
Area of Science:
- Neuromorphic Engineering
- Artificial Intelligence Hardware
Background:
- Spiking neural networks (SNNs) offer a power-efficient alternative to traditional artificial neural networks.
- Implementing large-scale SNNs on hardware presents challenges in terms of memory and power consumption.
Purpose of the Study:
- To develop a reconfigurable and scalable spiking neural network (SNN) processor.
- To investigate the effectiveness of deep compression techniques for SNN hardware.
Main Methods:
- A custom SNN processor with 192 neurons and 6144 synapses was designed and fabricated.
- A deep compression technique was applied to reduce the physical synapse requirement by a factor of 16.
- A 2-layer fully-connected SNN was mapped onto the developed chip.
Main Results:
- The deep compression technique maintained network accuracy while significantly reducing the need for SRAM and power consumption.
- The processor achieved a throughput of 1.1 GSOP/mm² at 1.2V and an energy efficiency of 35 pJ/SOP.
- Handwritten digit recognition on the MNIST dataset was performed with 91.2% accuracy.
Conclusions:
- The developed SNN processor demonstrates the feasibility of using deep compression for efficient neuromorphic hardware.
- The design offers a scalable and power-efficient solution for SNN implementation, suitable for tasks like digit recognition.
