A CMOS Low Pass Filter for SoC Lock-in-Based Measurement Devices

Area of Science:

• Electrical Engineering
• Analog Integrated Circuit Design
• Low Power Electronics

Background:

• Lock-in amplifiers are crucial for precise signal extraction in noisy environments.
• On-chip integration of filters demands high efficiency in terms of area and power consumption.
• Existing solutions often struggle to meet the stringent requirements for portable, multichannel systems.

Purpose of the Study:

• To present a fully integrated G-C low pass filter (LPF) for System-on-Chip (SoC) lock-in amplifier applications.
• To demonstrate a current steering G reduction-tuning technique for wideband frequency tunability.
• To validate the filter's performance in terms of power, area, and dynamic range for portable measurement systems.

Main Methods:

• Integration of first-order and second-order single-ended LPF topologies.
• Utilizing a 1.8 V to 0.18 µm CMOS process.
• Experimental validation of tuneable cutoff frequency, current consumption, size, and dynamic range.

Main Results:

• Achieved a tuneable cutoff frequency spanning five orders of magnitude (mHz to kHz).
• Demonstrated constant current consumption below 3 µA/pole.
• Exhibited compact size (<0.0140 mm²/pole) and a dynamic range exceeding 70 dB.
• Showcased competitive performance compared to state-of-the-art solutions.

Conclusions:

• The proposed G-C LPF meets the demanding requirements for on-chip portable measurement systems.
• The filter's efficiency in area and power is highly relevant for multichannel instruments and sensor arrays.
• This design offers a competitive solution for next-generation portable measurement instrumentation.