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A Parasitic Resistance-Adapted Programming Scheme for Memristor Crossbar-Based Neuromorphic Computing Systems.
1Faculty of Electrical and Electronics Engineering, Ho Chi Minh City University of Technology and Education, Ho Chi Minh City 70000, Vietnam.
Materials (Basel, Switzerland)
|December 11, 2019
Summary
This study introduces a new method to model wire resistance and a programming scheme to improve memristor crossbar circuits for neuromorphic computing. The proposed approach maintains high recognition rates even with significant wire resistance.
Area of Science:
- Neuromorphic Engineering
- Materials Science
Background:
- Memristor crossbar arrays offer a path to advanced neuromorphic computing systems.
- Wire resistance in these arrays significantly degrades circuit performance.
Purpose of the Study:
- To develop a wire resistance modeling method for memristor crossbar circuits.
- To propose a parasitic resistance-adapted programming scheme to mitigate wire resistance effects.
Main Methods:
- Equivalent wire resistances were estimated using the superposition theorem.
- A novel programming scheme updates the connection matrix to compensate for parasitic resistance.
- Circuit simulations validated the proposed methods.
Main Results:
- The proposed modeling method achieved a discrepancy of only 2.9% in output voltages compared to conventional methods.
- The parasitic resistance-adapted programming scheme maintained a 100% recognition rate at 3.0 Ω wire resistance, outperforming conventional schemes.
Conclusions:
- The developed wire resistance modeling and programming scheme effectively reduce the impact of wire resistance in memristor crossbar-based neuromorphic systems.
- This work enhances the feasibility of high-performance memristor crossbar circuits for neuromorphic applications.
