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Related Concept Videos

Design Example: Capacitance Multiplier Circuit01:20

Design Example: Capacitance Multiplier Circuit

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In integrated circuit technology, a capacitance multiplier is often utilized to produce a larger capacitance value when a small physical capacitance falls short. This is achieved by a circuit that multiplies capacitance values by a factor of up to 1000, such that a 10-pF capacitor can replicate the performance of a 100-nF capacitor.
The circuit illustrated in Figure 1 below incorporates two op-amps, with the first operating as a voltage follower and the second acting as an inverting amplifier.
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An Integrated Multi-Channel Biopotential Recording Analog Front-End IC With Area-Efficient Driven-Right-Leg Circuit.

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    |December 14, 2019
    PubMed
    Summary
    This summary is machine-generated.

    This study presents an area-efficient analog front-end (AFE) for biopotential recording, featuring an integrated driven-right-leg (DRL) circuit. The novel design significantly reduces chip area and enhances common-mode rejection ratio (CMRR) for improved signal quality.

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    Area of Science:

    • Biomedical Engineering
    • Analog Integrated Circuit Design
    • Wearable Health Technology

    Background:

    • Biopotential recording systems require high performance analog front-ends (AFEs) for accurate signal acquisition.
    • Existing AFEs often face challenges with power consumption, chip area, and common-mode rejection ratio (CMRR).
    • Integrated driven-right-leg (DRL) circuits are crucial for improving CMRR but can increase overall system size.

    Purpose of the Study:

    • To develop a multi-channel biopotential recording AFE with a fully integrated and area-efficient DRL circuit.
    • To enhance the system-level CMRR without compromising AFE performance.
    • To reduce the overall chip area of biopotential recording systems.

    Main Methods:

    • Designed a 10-channel low-noise capacitive coupled instrumentation amplifier (CCIA) based AFE.
    • Integrated a novel DRL circuit that reuses the AFE gain for improved efficiency.
    • Implemented the AFE and DRL circuit in a standard 0.18-μm CMOS process.
    • Utilized a shared 10-bit successive approximation register (SAR) analog-to-digital converter (ADC).

    Main Results:

    • Achieved over 85% chip area reduction for the DRL circuit compared to state-of-the-art.
    • Demonstrated a maximum of 60 dB enhancement in system-level CMRR.
    • Measured AFE gain of 60 dB/54 dB (high/low) with 1 μA/channel current consumption.
    • Obtained a low input-referred noise of 4.2 μVrms (1 Hz - 10 kHz).
    • Achieved a maximum system-level CMRR of 110 dB.

    Conclusions:

    • The proposed AFE with an integrated area-efficient DRL circuit offers significant advantages in terms of size and CMRR performance.
    • This design is suitable for low-power, high-performance biopotential recording applications.
    • The innovative DRL implementation effectively reduces circuit area and enhances signal quality.