An Energy-Quality Scalable STDP Based Sparse Coding Processor With On-Chip Learning Capability.

Area of Science:

• Neuromorphic Engineering
• Computer Science
• Electrical Engineering

Background:

• Implementing energy-efficient spike-timing-dependent plasticity (STDP) based sparse coding faces challenges with complex winner-take-all (WTA) operations and repetitive neuronal processing.
• Existing methods often lack computational efficiency, hindering practical applications.

Purpose of the Study:

• To develop a low-cost, energy-efficient hardware processor for STDP-based sparse coding.
• To address the computational bottlenecks in WTA operations and temporal processing.
• To enable dynamic trade-offs between algorithmic quality and energy consumption.

Main Methods:

• Algorithmic reduction techniques were employed to simplify the WTA operation through spike-emitting neuron prediction.
• Sparsity-based approximations in spatial and temporal domains were utilized to eliminate redundant neurons.
• Hardware implementation was performed using a 65nm CMOS process.

Main Results:

• The proposed Spiking Neural Network (SNN) architecture achieved up to 74% energy savings by exploiting input sparsity.
• Applications with natural images showed a maximum 0.01 RMSE increment, while MNIST applications had no accuracy loss.
• Inference mode yielded a throughput of 374 Mpixels/s and 840.2 GSOP/s, with energy efficiencies of 781.52 pJ/pixel and 0.35 pJ/SOP.

Conclusions:

• The developed hardware processor offers a significant reduction in energy consumption for STDP-based sparse coding.
• The approach effectively balances computational efficiency with minimal impact on algorithmic accuracy.
• This work presents a viable solution for energy-efficient neuromorphic computing applications.