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Related Concept Videos

Integration of Synaptic Events01:28

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Synaptic integration mainly includes the summation of graded potentials. Graded potentials, regardless of their type, cause subtle alterations in membrane voltage, resulting in either depolarization or hyperpolarization. These incremental changes, when combined or summed, can propel the neuron toward its threshold. Consider, for example, a membrane experiencing a +15 mV shift, causing it to depolarize from -70 mV to -55 mV. In this scenario, graded potentials govern the membrane's ability to...
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Neural circuits and neuronal pools are two of the main structures found in the nervous system. Neural circuits are networks of neurons that work together to carry out a specific task or process. They consist of interconnected neurons and glial cells, which provide structural and metabolic support.
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Interfacing 3D Engineered Neuronal Cultures to Micro-Electrode Arrays: An Innovative In Vitro Experimental Model
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3D Stackable Synaptic Transistor for 3D Integrated Artificial Neural Networks.

Seong Kwang Kim1, YeonJoo Jeong2, Pavlo Bidenko1

  • 1School of Electrical Engineering , Korea Advanced Institute of Science and Technology (KAIST) , Daejeon 34141 , Republic of Korea.

ACS Applied Materials & Interfaces
|January 16, 2020
PubMed
Summary
This summary is machine-generated.

Researchers developed 3D stackable synaptic transistors for artificial neural networks (ANNs) to reduce power consumption. This innovation minimizes interconnection energy use, paving the way for more efficient future computing systems.

Keywords:
III−Vartificial neural networkmonolithic 3D integrationneuromorphicsynapse

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Area of Science:

  • Materials Science
  • Computer Engineering
  • Electrical Engineering

Background:

  • Traditional artificial neural networks (ANNs) face significant power consumption challenges due to extensive data transmission in interconnections.
  • Minimizing power usage is crucial for the advancement of low-power computing and neuromorphic devices.

Purpose of the Study:

  • To propose and demonstrate the feasibility of 3D stackable synaptic transistors for creating energy-efficient 3D ANNs.
  • To address the power consumption issues in ANNs by reducing interconnection lengths.

Main Methods:

  • Developed monolithic 3D integration of synaptic devices utilizing a channel layer transfer method and wafer bonding.
  • Employed a low-temperature processible III-V and composite oxide (Al2O3/HfO2/Al2O3) material for the weight storage layer.

Main Results:

  • Successfully fabricated synaptic transistors exhibiting good linearity (αp/αd = 1.8/0.5) and a high transconductance ratio (6300).
  • Demonstrated excellent device stability and achieved a high learning accuracy of 97% on 1 million MNIST images.

Conclusions:

  • 3D stackable synaptic transistors offer a promising platform for future computing systems by enabling high integration density and reducing power consumption.
  • The developed monolithic 3D integration technique is feasible for creating advanced neuromorphic devices.