Facet-Dependent Surface Trap States and Carrier Lifetimes of Silicon

The facet-dependent electrical conductivity properties of silicon wafers result from significant band structure differences and variations in bond length, bond geometry, and frontier orbital electron distribution between the metal-like and semiconducting planes of silicon. To further understand the emergence of conductivity facet effects, electrochemical impedance measurements were conducted on intrinsic Si {100}, {110}, and {111} wafers. The attempt-to-escape frequency, obtained from temperature-dependent capacitance versus applied frequency curves, and other parameters derived from typical semiconductor property measurements were used to construct a diagram of the trap energy level (E_t) and the amount of trap states N_t(E_t). The trap states are located 0.61-0.72 eV above the silicon conduction band. Compared to {100} and {110} wafers, Si {111} wafer shows far less densities of trap states over the range of -0.2 to 2 V. Since these trap states inhibit direct electron excitation to the conduction band, the {111} wafer having much fewer trap states presents the best electrical conductivity property. Impedance data also provide facet-specific carrier lifetimes. The {111} surface gives consistently the lowest carrier lifetime, which reflects its high electrical conductivity. Lastly, ultraviolet photoelectron spectra and diffuse reflectance spectra were taken to obtain Schottky barriers between Ag and contacting Si wafers. The most conductive {111} surface presenting the largest Schottky barrier means the degrees of surface band bending used to explain facet-dependent electrical behaviors cannot be reliably attained this way.