Design and implementation of an ultra-low energy FFT ASIC for processing ECG in Cardiac Pacemakers

Area of Science:

• Biomedical Engineering
• Computer Engineering
• Signal Processing

Background:

• Fast Fourier Transform (FFT) algorithms are essential for pattern detection in embedded biomedical applications.
• Application-Specific Integrated Circuits (ASICs) are used in devices like cardiac pacemakers for low-power FFT computation.
• Existing FFT implementations face challenges in power efficiency for deeply embedded systems.

Purpose of the Study:

• To propose a data-driven design approach for an FFT ASIC tailored for embedded biomedical systems.
• To reduce the power consumption and energy footprint of FFT computations in cardiac pacemakers.
• To enhance battery life in implantable cardiac devices through optimized signal processing.

Main Methods:

• Developed a data-driven FFT ASIC design leveraging Hashing and Look-Up Tables (LUTs).
• Exploited the limited data range characteristic of embedded biomedical applications.
• Synthesized the design using a 90nm standard cell library and simulated gate-level switching activity for power analysis.

Main Results:

• Achieved a significant reduction in arithmetic operations for ECG signal processing.
• Demonstrated a low energy consumption of 27.72nJ per FFT computation.
• Attained a 14.22% reduction in energy consumption compared to a standard 128-point radix-2 FFT.

Conclusions:

• The proposed Hashing and LUT-based FFT ASIC design offers substantial power savings for embedded biomedical applications.
• This optimization is crucial for extending battery life in critical devices such as cardiac pacemakers.
• The data-driven approach provides an effective strategy for energy-efficient signal processing in resource-constrained environments.