Resource Shared Galois Field Computation for Energy Efficient AES/CRC in IoT Applications

Modern smart devices require robust data protection and error detection to function reliably in connected environments. Current industry standards rely heavily on Advanced Encryption Standard and Cyclic Redundancy Check protocols for these tasks. Dedicated hardware engines often handle these functions separately within embedded systems on chips. This separation leads to increased silicon footprint and higher power usage in constrained environments. No prior work had resolved the inefficiency of maintaining independent processing blocks for these two distinct operations. That uncertainty drove the need for a unified approach to hardware resource management. This paper addresses the challenge of integrating these functions without excessive energy expenditure. The researchers propose a novel architecture to optimize hardware utilization for low-power applications.

The aim of this study is to design an energy-efficient multipurpose engine for processing both AES and CRC algorithms. These two standards are essential for security and reliability in modern smart devices. Current implementations often rely on separate co-processors that consume excessive silicon area and battery power. This inefficiency poses a significant challenge for ultralow-power embedded System on Chips. The researchers seek to resolve this by identifying shared mathematical operations within the two protocols. They propose a unified architecture to handle both tasks using a single computation unit. This motivation stems from the need to reduce the physical and electrical footprint of security hardware. The study focuses on developing a resource-shared system that maintains performance while optimizing power usage.

The researchers employed a hardware design approach focused on architectural optimization for embedded systems. They performed a mathematical decomposition of the required algorithms to isolate common binary operations. This analysis enabled the creation of a unified processing engine. The team utilized a 90nm technology node for the physical implementation of the proposed system. They measured the silicon area occupied by the final hardware layout. Performance testing involved evaluating the throughput of the shared unit under specific voltage conditions. The investigators calculated energy consumption metrics for both encryption and error detection tasks. This methodology allowed for a direct comparison between the shared architecture and traditional, independent hardware designs.

The shared computation unit successfully processes both AES-128 and CRC-32 algorithms within a compact 151μm x 151μm area. Operating at a 0.8 V supply voltage, the design achieves a throughput of 25.6 Mbps. Energy consumption for AES-128 encryption is measured at less than 280pJ per operation. For CRC-32 tasks, the energy requirement is even lower, at less than 140pJ. These values demonstrate a significant reduction in power usage compared to separate dedicated engines. The implementation confirms that binary-level sharing of Galois Field operations is feasible for these standards. The findings indicate that the unified engine maintains high performance while minimizing silicon footprint. This result validates the effectiveness of the proposed resource-sharing architecture for low-power applications.

The authors demonstrate that sharing computational resources significantly reduces the physical footprint of security hardware. This synthesis suggests that unified architectures provide a viable path for energy-constrained smart device design. The findings imply that decomposing complex mathematical operations reveals hidden commonalities between disparate algorithms. Implementing these shared units allows for substantial savings in power consumption during standard encryption and verification tasks. The study confirms that a single engine can effectively handle both AES-128 and CRC-32 processing requirements. These results indicate that hardware efficiency gains are achievable through strategic architectural integration. The researchers conclude that their approach maintains necessary performance levels while minimizing silicon area usage. This work offers a practical framework for future developments in low-power embedded system design.