Design and implementation of an ultra-low energy FFT ASIC for processing ECG in Cardiac Pacemakers

In embedded biomedical applications, spectrum analysis algorithms such as Fast Fourier Transform (FFT) are crucial for pattern detection and has been the focus of continued research. In deeply embedded systems such as cardiac pacemakers, FFT based signal processing is typically computed by Application Specific Integrated Circuits (ASIC) to achieve low power operation. This research proposes a data driven design approach for an FFT ASIC solution which exploits the limited range of data encountered by these embedded systems. The optimizations proposed in this paper uses the simple concept of Hashing and Look-Up Tables (LUT) to effectively reduce the number of arithmetic operations required to perform the FFT of an electrocardiogram (ECG) signal. By reducing the dynamic power consumption and overall energy footprint of FFT computation, the proposed design aims to achieve longer battery life for a Cardiac Pacemaker. The design is synthesized using a 90nm standard cell library, and gate level switching activity is simulated to obtain accurate power consumption results. The proposed optimizations achieved a low energy consumption of 27.72nJ per FFT, which is 14.22% lower than a standard 128-point radix-2 FFT when tested with actual ECG data collected from PhysioNet.