A Highly Linear CMOS Image Sensor Design Based on an Adaptive Nonlinear Ramp Generator and Fully Differential...

Area of Science:

• Electrical Engineering
• Materials Science
• Image Processing

Background:

• Complementary metal-oxide-semiconductor (CMOS) image sensors require advanced techniques for linearity, low noise, and high frame rates.
• Pixel non-linearity, caused by source follower transistors and integration capacitors, degrades image quality.
• High column fixed pattern noise and limited frame rates are persistent challenges in CMOS image sensor design.

Purpose of the Study:

• To propose an adaptive nonlinear ramp generator circuit to mitigate pixel unit circuit non-linearity.
• To introduce a novel readout scheme for enhanced frame rates and reduced column fixed pattern noise.
• To improve the overall performance of CMOS image sensors, focusing on linearity and noise reduction.

Main Methods:

• An adaptive nonlinear ramp generator circuit based on dummy pixels in a single-slope analog-to-digital converter topology was developed.
• A fully differential pipeline sampling quantization with a double auto-zeroing technique was implemented for the readout scheme.
• The proposed techniques were simulated and verified using a prototype chip fabricated with 180 nm CMOS technology.

Main Results:

• Overall non-linearity in the CMOS image sensor was reduced from 1.03% to 0.047%.
• Comparator efficiency was improved from 85.3% to a perfect 100%.
• Column fixed pattern noise was significantly reduced from 0.43% to 0.019%.

Conclusions:

• The proposed adaptive nonlinear ramp generator effectively mitigates gain non-linearity in source follower transistors and integration capacitors.
• The new readout scheme enhances frame rates and improves comparator consistency, drastically reducing column fixed pattern noise.
• The developed techniques offer a substantial improvement in CMOS image sensor performance, achieving high linearity and low noise.