A Simulation Study of a Gate-All-Around Nanowire Transistor with a Core-Insulator

Area of Science:

• Semiconductor physics
• Materials science
• Nanoelectronics

Background:

• Scaling of complementary metal oxide semiconductor field effect transistors (CMOSFETs) is crucial for energy-efficient and portable electronics.
• Reducing off-state leakage current in MOSFETs is a key challenge for device miniaturization.
• Nanowire structures show promise for next-generation logic devices due to potentially lower off-state currents than FinFETs.

Purpose of the Study:

• To propose and investigate a novel Core-Insulator Gate-All-Around (CIGAA) nanowire structure.
• To comprehensively evaluate the performance of CIGAA nanowires using 3D numerical simulations.
• To compare the off-state current characteristics of CIGAA nanowires against traditional Gate-All-Around (GAA) nanowires.

Main Methods:

• 3D numerical simulation of semiconductor device physics.
• Design and modeling of the novel CIGAA nanowire architecture.
• Comparative analysis of electrical performance metrics between CIGAA and GAA structures.

Main Results:

• The proposed CIGAA nanowire structure demonstrates a lower off-state current compared to the conventional GAA nanowire.
• Simulations confirm the effectiveness of the CIGAA design in suppressing leakage currents.
• The CIGAA structure shows potential for enhanced performance in low-power applications.

Conclusions:

• The CIGAA nanowire is a promising candidate for future low-power, energy-efficient logic devices.
• The reduced off-state current of CIGAA structures addresses a critical challenge in semiconductor scaling.
• Further exploration of nanowire architectures like CIGAA is essential for advancing nanoelectronic devices.