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Parallel Processing

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Related Experiment Video

Updated: Dec 26, 2025

High-Throughput Analysis of Optical Mapping Data Using ElectroMap

High-Throughput Analysis of Optical Mapping Data Using ElectroMap

Published on: June 4, 2019

SOMprocessor: A high throughput FPGA-based architecture for implementing Self-Organizing Maps and its application to

Miguel Angelo de Abreu de Sousa¹, Ricardo Pires¹, Emilio Del-Moral-Hernandez²

¹Electrical Department, Federal Institute of Education, Science and Technology of Sao Paulo - IFSP, Sao Paulo, Brazil.

Neural Networks : the Official Journal of the International Neural Network Society

|March 18, 2020

Summary

This study introduces a novel FPGA architecture, SOMprocessor, for efficient hardware implementation of Self-Organizing Maps (SOMs). The design accelerates unsupervised learning for real-time applications, achieving significant performance gains over CPU execution.

Keywords:

FPGA Neuromorphic chip Self-organizing Maps Unsupervised learning Video surveillance

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Last Updated: Dec 26, 2025

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Area of Science:

Neuromorphic Engineering
Artificial Intelligence
Computer Architecture

Background:

Neuromorphic chips aim to accelerate artificial neural networks through parallel processing.
Unsupervised learning models like Self-Organizing Maps (SOMs) require efficient hardware for real-time and embedded systems.

Purpose of the Study:

To present a theoretical analysis of hardware-based SOM algorithms.
To detail a novel FPGA architecture, SOMprocessor, for enhanced SOM computation.
To evaluate the performance and accuracy of the SOMprocessor.

Main Methods:

Theoretical analysis of SOM learning and recall algorithms for hardware implementation.
Design and implementation of the SOMprocessor FPGA architecture with novel computational strategies.
Application of SOMprocessor to a video categorization task for performance evaluation.

Main Results:

The SOMprocessor architecture explores computational strategies to improve data flow and flexibility.
Hardware and software implementations of SOMs show similar topographic and quantization errors.
The FPGA architecture achieves a 3-4 order of magnitude acceleration compared to CPU execution.

Conclusions:

The SOMprocessor offers a significant acceleration for SOM-based unsupervised learning on FPGAs.
The proposed architecture is suitable for real-time and embedded applications requiring efficient neural network processing.
Hardware implementation of SOMs can match software accuracy while providing substantial performance benefits.