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Published on: January 19, 2018
Cluster-Type Filaments Induced by Doping in Low-Operation-Current Conductive Bridge Random Access Memory.
Yiming Sun1, Cheng Song1, Siqi Yin1
1Key Laboratory of Advanced Materials (MOE), School of Materials Science and Engineering, Tsinghua University, Beijing 100084, China.
This study introduces a novel conductive bridge random access memory (CBRAM) structure enabling low-power operation at ~1 μA. The research demonstrates a five-resistance-state multilevel cell, paving the way for efficient, high-density memory integration.
Area of Science:
- Materials Science
- Electrical Engineering
- Nanotechnology
Background:
- Conductive bridge random access memory (CBRAM) offers high speed, density, and power efficiency.
- Resistive switching in CBRAM relies on metallic conductive filament formation/rupture via cation migration and redox processes.
- Current research aims to reduce operation current for low-power consumption and improve reliability.
Purpose of the Study:
- To propose and investigate a novel Pt/TaOx:Ag/TaOx/Pt structure for CBRAM.
- To achieve nonvolatile switching at significantly low currents (~1 μA).
- To demonstrate multilevel cell operation with five resistance states.
Main Methods:
- Fabrication of a novel Pt/TaOx:Ag/TaOx/Pt memory device structure.
- Characterization of resistive switching behaviors under varying compliance currents.
- Analysis of conductive filament morphology using electron microscopy (implied).
Main Results:
- Achieved nonvolatile switching at approximately 1 μA operation current.
- Demonstrated a five-resistance-state multilevel cell operation.
- Observed cluster-type conductive filaments, distinct from traditional nanocone structures, explaining low-current switching.
- Cu-doped devices exhibited similar promising characteristics.
Conclusions:
- The novel CBRAM structure enables ultra-low power consumption memory devices.
- The observed cluster-type filaments are key to achieving low-operation current resistive switching.
- This technology offers feasibility for large-scale memory crossbar integration and advanced computing.
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