A High-Speed Low-Cost VLSI System Capable of On-Chip Online Learning for Dynamic Vision Sensor Data Classification

Area of Science:

• Neuromorphic Engineering
• Computer Vision Hardware

Background:

• Dynamic Vision Sensors (DVS) generate event-based data (address-event representation, AER) that requires efficient processing.
• On-chip learning capabilities are crucial for adapting neuromorphic systems to diverse real-world applications.

Purpose of the Study:

• To develop a high-speed, low-cost VLSI system for real-time classification of AER streams from DVS.
• To enable on-chip online learning for flexible adaptation to different application scenarios.

Main Methods:

• Implementation of a lightweight statistical algorithm using binary features and a Random Ferns classifier.
• Design of a memory-centric VLSI architecture with multi-level pipelines and parallel processing.
• Development of an FPGA prototype on a Xilinx Zynq-7045 platform.

Main Results:

• Achieved a peak processing throughput of 100 Meps (Mega events per second) at 100 MHz.
• Demonstrated high energy efficiency of 145 Meps/W (145 event/μJ) with low resource utilization (<11%).
• Attained classification accuracies of 77.9% (MNIST-DVS), 99.4% (Poker-DVS), and 99.3% (Posture-DVS).

Conclusions:

• The proposed VLSI system offers superior processing speeds and energy efficiency compared to existing methods.
• The system's low-cost, memory-centric design and on-chip learning capability make it suitable for embedded neuromorphic applications.
• This work advances the development of efficient hardware for event-based vision processing.