An Edge On-Chip-Learning Convolutional Spiking Neural Network Processor Based on Error Backpropagation via...

Area of Science:

• Neuromorphic Engineering
• Artificial Intelligence
• Computer Architecture

Background:

• Spiking Neural Networks (SNNs) provide energy efficiency for edge computing but face challenges in on-chip backpropagation for convolutional networks.
• Current hardware often uses offline training or local rules, limiting complex feature extraction.

Purpose of the Study:

• To present a convolutional SNN processor with ConvTempo, an end-to-end global optimization framework for efficient on-chip learning.
• To address memory and logic overhead challenges in implementing backpropagation for SNNs.

Main Methods:

• ConvTempo restricts neurons to fire once, enabling sparse surrogate-gradient backpropagation at peak membrane potential to minimize computation.
• An Output Channel-First (OC-First) mechanism reduces state storage, and a Time-Channel Indexed cache compacts spike-event data.

Main Results:

• The processor, prototyped on an FPGA, achieved significant accuracy improvements (0.64%-2.69%) over an STDP baseline on benchmark datasets.
• It demonstrated low power consumption (0.589 W) and efficient resource utilization (8 DSPs, 94.5 BRAMs).

Conclusions:

• The ConvTempo framework offers a high-accuracy, on-chip learning solution for resource-constrained edge applications.
• It overcomes previous limitations by enabling global backpropagation with competitive logic resource utilization.