Mach-RT: A Many Chip Architecture for High Performance Ray Tracing.

Area of Science:

• Computer Architecture
• Computer Graphics
• High-Performance Computing

Background:

• Data movement, especially main memory access, is a significant bottleneck in computing, including ray tracing.
• Existing architectures struggle to efficiently manage scene data access for complex rendering tasks.

Purpose of the Study:

• To introduce Mach-RT, a many-chip hardware architecture designed to accelerate ray tracing.
• To address the memory access bottleneck in ray tracing through an unconventional solution.

Main Methods:

• Implementing a ray ordering scheme to minimize scene data access.
• Utilizing a large on-chip buffer as near-compute storage distributed across multiple chips.
• Extending dual streaming concepts to optimize main memory accesses for multiple processor chips concurrently.

Main Results:

• Mach-RT demonstrates significant performance increases compared to existing architectures.
• The architecture achieves performance gains while maintaining reasonable energy consumption due to reduced memory traffic.
• Design space exploration of L3 cache size and detailed energy/memory performance evaluations are presented.

Conclusions:

• Mach-RT offers an effective solution for accelerating ray tracing by optimizing memory access patterns.
• The many-chip architecture provides a scalable and energy-efficient approach to high-performance ray tracing.
• This work extends previous research with enhanced analysis and new predictive scheduling logic.