Cost-optimized heterogeneous FPGA architecture for non-iterative hologram generation

Area of Science:

• Computer engineering
• Optics
• Digital signal processing

Background:

• Computer-generated holograms (CGHs) demand substantial computational resources.
• Field-programmable gate arrays (FPGAs) offer parallel processing capabilities suitable for accelerating CGH generation algorithms.
• Non-iterative algorithms are preferred for real-time or high-speed CGH synthesis.

Purpose of the Study:

• To present a cost-optimized heterogeneous FPGA architecture for non-iterative CGH generation.
• To evaluate the performance and cost-effectiveness of the proposed hardware implementation.
• To demonstrate the feasibility of integrating the architecture into compact display systems.

Main Methods:

• Implementation of a one-step phase retrieval algorithm on a heterogeneous FPGA architecture.
• Design of a parallel processing architecture optimized for computational efficiency.
• Performance comparison against a high-end multi-core CPU software implementation.

Main Results:

• The FPGA hardware implementation achieved a 2.5x speed improvement compared to the software baseline.
• Demonstrated trade-offs between hardware cost and computational performance.
• Validated the suitability of the architecture for compact, cost-optimized display systems.

Conclusions:

• The proposed heterogeneous FPGA architecture provides a significant acceleration for CGH generation.
• This approach offers a viable solution for real-time holographic display applications.
• The system is optimized for both cost and size, enabling practical deployment.