Fault-Tolerant Network-On-Chip Router Architecture Design for Heterogeneous Computing Systems in the Context of...

Area of Science:

• Computer Engineering
• Fault-Tolerant Systems
• VLSI Design

Background:

• Network-on-Chip (NoC) architectures are crucial for scalable, high-performance heterogeneous computing.
• Technology scaling increases the susceptibility of NoCs to permanent and transient faults.
• Permanent faults in NoC routers degrade overall network performance, necessitating robust protection mechanisms.

Purpose of the Study:

• To develop and evaluate a novel fault-tolerant Network-on-Chip (NoC) router design.
• To enhance the resilience of NoC routers against permanent faults.
• To quantify the reliability and protection capabilities of the proposed router design.

Main Methods:

• Implemented component-level protection techniques including bypass paths, virtual channel (VC) queuing, and VC closing at input ports.
• Employed spatial redundancy and double routing in the routing computation stage.
• Utilized spatial redundancy in the VC allocation stage and run-time arbiter selection in the switch allocation stage.
• Incorporated a triple bypass bus in the crossbar stage.

Main Results:

• The proposed router demonstrates significantly higher fault tolerance compared to existing state-of-the-art designs.
• Achieved a 7.98 times higher mean-time-to-failure (MTTF) compared to an unprotected baseline router.
• The silicon protection factor metric confirms superior protection ability over conventional fault-tolerant routers.

Conclusions:

• The proposed fault-tolerant NoC router effectively mitigates the impact of permanent faults.
• The integrated protection strategies result in substantial improvements in reliability and protection.
• This design offers a promising solution for enhancing the robustness of heterogeneous computing systems.