An Accelerator Design Using a MTCA Decomposition Algorithm for CNNs.

Area of Science:

• Computer Engineering
• Artificial Intelligence
• Hardware Acceleration

Background:

• Convolutional Neural Networks (CNNs) demand efficient hardware accelerators due to high throughput and computational needs.
• Existing methods like image to column (im2col) face challenges with intermediate matrix blocking and storage efficiency.

Purpose of the Study:

• To propose a novel block parallel computing algorithm for CNN hardware accelerators.
• To optimize convolution expansion and address intermediate matrix blocking issues.
• To enhance hardware storage efficiency and computational performance.

Main Methods:

• Developed a block parallel computing algorithm based on the Matrix Transformation Computing Algorithm (MTCA).
• Introduced an optimal matrix multiplication partitioning method for performance tuning.
• Implemented the algorithm within a dedicated accelerator architecture framework on FPGA.

Main Results:

• Achieved significant hardware storage reduction: over 60% compared to im2col, and nearly 82% for large-scale convolutions.
• Realized performance of 26.7–33.4 GFLOPS on FPGA by minimizing bandwidth and maximizing data reuse.
• Demonstrated 1.2×–4.0× speedup over memory-efficient convolution (MEC) and im2col.

Conclusions:

• The proposed MTCA-based algorithm offers an effective solution for large-scale CNN convolution acceleration.
• The method significantly improves storage efficiency and computational performance on hardware accelerators.
• This approach enables high parallel implementation and enhanced data reusability for CNNs.