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A Novel Hardware-Software Co-Design and Implementation of the HOG Algorithm.

Sina Ghaffari1, Parastoo Soleimani1, Kin Fun Li1

  • 1Department of Electrical and Computer Engineering, University of Victoria, Victoria, BC V8W 2Y2, Canada.

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Summary
This summary is machine-generated.

This study presents a hardware-software co-design for the histogram of oriented gradients (HOG) and support vector machine (SVM) classifier, optimizing resource usage and speed for image processing. The efficient design achieves high frame rates on an FPGA with minimal accuracy loss.

Keywords:
FPGA resource usageaccuracy lossbin assignmentframe ratehardware–software co-designhistogram of oriented gradients

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Area of Science:

  • Computer Engineering
  • Image Processing
  • Hardware Acceleration

Background:

  • The histogram of oriented gradients (HOG) is a vital feature extraction algorithm.
  • HOG's computational intensity necessitates hardware acceleration for improved performance.
  • Existing methods often face trade-offs between speed, resource usage, and accuracy.

Purpose of the Study:

  • To propose a hardware-software co-design for HOG and support vector machine (SVM) classifier.
  • To minimize hardware resource utilization while preserving accuracy and speed.
  • To enable efficient processing of data from digital image sensors.

Main Methods:

  • Offloading computationally intensive HOG steps (gradient calculation, magnitude, bin assignment, normalization, classification) to hardware.
  • Utilizing a logarithm-based bin assignment strategy.
  • Implementing parallel computation and time-sharing for histogram generation, achieving one pixel per clock cycle throughput.
  • Employing simplified block normalization logic for reduced hardware footprint.

Main Results:

  • Achieved a frame rate of 115 frames per second on a Xilinx Kintex Ultrascale FPGA.
  • Demonstrated reduced hardware resource usage compared to existing approaches.
  • Maintained high accuracy with only marginal loss.

Conclusions:

  • The proposed hardware-software co-design offers an efficient solution for HOG and SVM acceleration.
  • This design balances performance, resource efficiency, and accuracy for real-time image processing applications.
  • The optimized approach is suitable for deployment on Field-Programmable Gate Arrays (FPGAs).