A Scalable and Low Stress Post-CMOS Processing Technique for Implantable Microsensors.

Area of Science:

• Biomedical Engineering
• Materials Science
• Microfabrication

Background:

• Implantable active electronic microchips are crucial for in-body sensing and actuation.
• Current microfabrication techniques struggle with post-processing of small, bare complementary metal-oxide-semiconductor (CMOS) dies for physiological compatibility.

Purpose of the Study:

• To develop a scalable, low-stress microchip post-processing method for bare CMOS dies.
• To enable photolithography and electrode integration on miniature chips for implantable applications.

Main Methods:

• Utilized a polydimethylsiloxane (PDMS) carrier substrate for embedding and aligning CMOS chips.
• Enabled batch post-processing, including photolithography and electron-beam deposition of gold and PEDOT:PSS electrodes.
• Tested with 650 μm × 650 μm and 280 μm × 280 μm CMOS chips.

Main Results:

• Successfully demonstrated photolithography and electrode integration on sub-millimeter CMOS dies.
• Assessed electrical properties of integrated gold and PEDOT:PSS electrodes.
• Verified functionality in saline and ex vivo experiments using wireless power and data transmission.

Conclusions:

• The presented PDMS-based method offers a scalable and effective approach for post-processing miniature CMOS chips.
• This technique facilitates the creation of physiologically compatible implant ensembles for neural recording and stimulation.
• The microscale electrode interfaces show promising performance for in-body electronic applications.