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Related Experiment Video

Updated: Dec 6, 2025

Silicon Metal-oxide-semiconductor Quantum Dots for Single-electron Pumping
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Fabrication process and failure analysis for robust quantum dots in silicon.

J P Dodson1, Nathan Holman1, Brandur Thorgrimsson1

  • 1Department of Physics, University of Wisconsin-Madison, Madison, WI 53706, United States of America.

Nanotechnology
|October 12, 2020
PubMed
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We developed a new fabrication process for quantum dot devices, reducing electrical shorts and improving reliability. This method enhances the performance and durability of silicon-germanium heterostructure devices.

Area of Science:

  • Quantum computing and solid-state physics
  • Semiconductor device fabrication
  • Materials science for electronic devices

Background:

  • Quantum dot devices are crucial for quantum computing and advanced electronics.
  • Fabrication challenges include gate leakage, electrostatic discharge (ESD) damage, and material dewetting.
  • Optimizing fabrication is key to improving device performance and yield.

Purpose of the Study:

  • To present an improved fabrication process for overlapping aluminum gate quantum dot devices on Si/SiGe heterostructures.
  • To address and mitigate common issues such as gate leakage, ESD damage, and interconnect problems.
  • To investigate the impact of device geometry on gate electrode morphology and device reliability.

Main Methods:

  • Incorporation of low-temperature inter-gate oxidation and thermal annealing of gate oxide.

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Related Experiment Videos

Last Updated: Dec 6, 2025

Silicon Metal-oxide-semiconductor Quantum Dots for Single-electron Pumping
14:58

Silicon Metal-oxide-semiconductor Quantum Dots for Single-electron Pumping

Published on: June 3, 2015

15.2K
Nanofabrication of Gate-defined GaAs/AlGaAs Lateral Quantum Dots
15:47

Nanofabrication of Gate-defined GaAs/AlGaAs Lateral Quantum Dots

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Measurement of Quantum Interference in a Silicon Ring Resonator Photon Source
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  • Implementation of on-chip electrostatic discharge (ESD) protection.
  • Development of an optimized interconnect process considering thermal budget limitations.
  • Utilizing cross-sectional scanning transmission electron microscopy (STEM) for morphological analysis.

    • Main Results:

    • Reduced gate-to-gate leakage and damage from ESD.
    • Minimized dewetting of aluminum and formation of undesired alloys in interconnects.
    • Demonstrated homogeneous conformation of overlapping aluminum gate layers to underlying topology.
    • Identified critical gate geometry dimensions leading to non-ideal pattern transfer and device failure.

    Conclusions:

    • The improved fabrication process enhances the reliability and performance of Si/SiGe quantum dot devices.
    • Understanding gate electrode morphology through STEM is vital for optimizing device design.
    • The study provides critical insights for fabricating robust and high-yield quantum dot devices.