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Analysis of a Lateral Grain Boundary for Reducing Performance Variations in Poly-Si 1T-DRAM.

Songyi Yoo1,2, Wookyung Sun3, Hyungsoon Shin1,2

  • 1Department of Electronic and Electrical Engineering, Ewha Womans University, Seoul 03760, Korea.

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Summary

Capacitorless poly-silicon 1T-DRAM offers a solution to scaling limits by trapping charge at grain boundaries. Optimizing grain boundary location enhances memory performance and reliability, crucial for next-generation memory devices.

Keywords:
1T-DRAMGB locationcapacitorless one-transistor dynamic random-access memorygrain boundarylateral grain boundary (GB)polysilicon

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Area of Science:

  • Materials Science
  • Electrical Engineering
  • Semiconductor Physics

Background:

  • Conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM) faces scaling limitations.
  • Capacitorless one-transistor dynamic random-access memory (1T-DRAM) using a poly-silicon body (poly-Si) is proposed as an alternative.
  • Poly-Si 1T-DRAM utilizes charge trapped at grain boundaries (GBs) for memory operation.

Purpose of the Study:

  • Investigate the impact of lateral grain boundary location on poly-Si 1T-DRAM performance.
  • Determine the optimal lateral GB location for maximizing sensing margin and retention time.
  • Analyze the effect of lateral GBs on device reliability concerning random vertical GB placement.

Main Methods:

  • Technology Computer-Aided Design (TCAD) device simulations were employed.
  • Simulations systematically varied the lateral GB location within the poly-Si body.
  • Performance metrics including sensing margin and retention time were evaluated.

Main Results:

  • The operating mechanism and memory performance are sensitive to the lateral GB location due to altered charge trapping.
  • An optimal lateral GB location was identified to achieve superior sensing margin and retention time.
  • Devices with a lateral GB exhibit robust performance irrespective of random vertical GB placement, unlike devices without lateral GBs.

Conclusions:

  • The lateral GB location critically influences poly-Si 1T-DRAM performance.
  • Strategic placement of lateral GBs can optimize memory characteristics.
  • Poly-Si 1T-DRAM devices incorporating lateral GBs demonstrate enhanced reliability and tolerance to fabrication variations in vertical GBs.