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Incremental column-wise verification of arithmetic circuits using computer algebra.

Daniela Kaufmann1, Armin Biere1, Manuel Kauers2

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Formal Methods in System Design
|December 7, 2020
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Summary
This summary is machine-generated.

Verifying arithmetic circuits, especially multipliers, is automated using polynomial reasoning and Gröbner bases. Novel techniques improve efficiency and enable equivalence checking for bit-level multipliers.

Keywords:
Arithmetic circuit verificationComputer algebraGröbner basis

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Area of Science:

  • Computer Science
  • Formal Methods
  • Digital Circuit Verification

Background:

  • Manual verification of arithmetic circuits, particularly multipliers, is time-consuming and error-prone.
  • Existing methods rely on polynomial reasoning over pseudo-boolean polynomials and Gröbner bases for circuit verification.
  • A word-level specification is reduced by a Gröbner basis derived from the gate-level circuit representation.

Purpose of the Study:

  • To provide a rigorous formalization of the polynomial-based circuit verification approach, including soundness and completeness.
  • To introduce novel, incremental, and column-wise techniques for verifying gate-level multipliers.
  • To extend algebraic verification methods to bit-level multiplier equivalence checking without word-level specifications.

Main Methods:

  • Formalizing the Gröbner basis reduction approach for arithmetic circuit verification.
  • Developing an incremental, column-wise verification technique for gate-level multipliers.
  • Extracting full- and half-adder constraints to optimize Gröbner basis reduction.
  • Presenting a new theorem for rewriting local parts of Gröbner bases.
  • Extending algebraic techniques for bit-level multiplier equivalence verification.

Main Results:

  • The Gröbner basis reduction approach is rigorously formalized with soundness and completeness proofs.
  • The novel incremental column-wise technique significantly improves the efficiency of multiplier verification.
  • Optimizing the Gröbner basis through constraint extraction and rewriting substantially reduces computation time.
  • The extended algebraic techniques successfully verify the equivalence of bit-level multipliers.
  • Experiments demonstrate efficient verification of regular multipliers with standard tools, while optimized multipliers require advanced methods.

Conclusions:

  • The formalized polynomial-based approach provides a robust framework for arithmetic circuit verification.
  • The developed incremental and optimization techniques offer significant performance improvements.
  • The extended methods enable verification of multiplier equivalence at the bit-level.
  • The study highlights the scalability and effectiveness of algebraic techniques in digital circuit verification.