Exceedingly High Performance Top-Gate P-Type SnO Thin Film Transistor with a Nanometer Scale Channel Layer

Area of Science:

• Materials Science
• Semiconductor Physics
• Electronics Engineering

Background:

• High-performance thin-film transistors (TFTs) are essential for advanced integrated circuits (ICs) and displays.
• Top-gate structures are preferred for monolithic 3D ICs, but achieving high-performance p-type TFTs (p-TFTs) is challenging.
• Key parameters like hole mobility (μ) and on/off current ratio (I_ON/I_OFF) are difficult to optimize in top-gate p-TFTs.

Purpose of the Study:

• To develop high-performance coplanar top-gate tin oxide (SnO) p-TFTs.
• To investigate the impact of process temperature and oxygen content on device performance.
• To achieve simultaneously high hole mobility, large I_ON/I_OFF ratio, and sharp subthreshold slopes (SS).

Main Methods:

• Fabrication of coplanar top-gate nanosheet SnO p-TFTs.
• Secondary ion mass spectrometry (SIMS) analysis to study interface integrity and inter-diffusion.
• Systematic investigation of process temperature and oxygen content effects.

Main Results:

• Achieved a high hole field-effect mobility (μ) of 4.4 cm²/Vs.
• Obtained a large on/off current ratio (I_ON/I_OFF) of 1.2 × 10⁵.
• Demonstrated sharp transistor turn-on subthreshold slopes (SS) of 526 mV/decade.
• Identified process temperature and oxygen content as critical factors affecting device performance due to Sn/Hf inter-diffusion and SnO oxidation.

Conclusions:

• The developed SnO p-TFTs exhibit the best reported performance for top-gate p-TFTs to date.
• Optimized process conditions minimize inter-diffusion and prevent channel oxidation, ensuring device integrity.
• These findings facilitate the development of monolithic 3D ICs on the backend dielectric of IC chips.