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This study addresses gate to elevated source-drain (eSD) shorts, a key FinFET defect. A smart manufacturing platform improved yield by 25.2% without compromising device performance.

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Area of Science:

  • Semiconductor manufacturing
  • Advanced materials science
  • Process engineering

Background:

  • Transition from 2D planar to 3D FinFET technology is accelerating.
  • Merged elevated source-drain (eSD) epi structures are crucial for FinFET performance enhancement, particularly in reducing Rsd.
  • Existing research on eSD defects lacks focus on yield impact and systematic defect detection in complex 3D structures.

Purpose of the Study:

  • Investigate the root cause of gate to eSD shorts, the main detractor of FinFET yield.
  • Develop and implement a smart manufacturing (SM) solution to enhance FinFET yield.
  • Optimize the eSD process for improved yield without performance degradation.

Main Methods:

  • Utilized an in-house smart manufacturing (SM) platform with four integrated modules: virtual integration (VI), hot spot identification, advanced analytics, and co-optimization.
  • Employed algorithms for defect definition, process control, feature selection, and fail bit prediction.
  • Focused on identifying and resolving systematic defects in complex 3D FinFET structures.

Main Results:

  • Identified the root cause of gate to eSD shorts, a critical FinFET yield issue.
  • Achieved a significant yield improvement of 25.2% through the implemented SM solution.
  • Demonstrated that yield enhancement did not negatively impact device performance.

Conclusions:

  • The developed smart manufacturing platform effectively addresses complex 3D structure defects in FinFETs.
  • Systematic defect analysis and targeted process optimization are key to improving semiconductor manufacturing yield.
  • The study provides a viable solution for enhancing FinFET production efficiency and reliability.